Multiple bank memory circuits call for new and innovative solutions to maximize device performance while minimizing chip size. In attempting to meet this demand, circuit designers have proposed numerous alternatives to the standard synchronous DRAM ("SDRAMs") architecture. Unfortunately, meeting the higher density has proven mutually exclusive with meeting the higher speed requirements. Circuitry to accelerate data flow tends to add area to the memory device. This may be due to increased parallelism where more memory bits are accessed per access. Also, increased area may come from using complex sequences of accelerated data flows in employing a "pipeline" scheme where data is sequentially transmitted down a logically segmented data path.
The area penalty associated with these techniques prevent their unequivocal acceptance, because these penalties directly translate into higher device costs and lower profit margins. Consequently, demand still remains for high speed and density memory device that can compete with the standard asynchronous DRAMs in terms of device size and circuit complexity.
One particular problem with more dense circuits that the present invention addresses relates to the row and column path complexities and size increases that occur as a memory array is partitioned into banks. The row path circuit must latch the wordline for each activated bank, with each bank demanding its own Y-decoder circuit, which increases the device size and affects device performance. For example, a four-bank 256 MB SDRAM requires row address latches for each of four banks in order to hold the wordline state and four Y-decoder banks to complete the column path. This increased complexity consumes circuit area on integrated circuits and generally increases the complexity of the synchronous DRAM.
One of the significant consumers of circuit area is the Y-decoder circuit for transforming column factor signals into Y-select signals for accessing cells in a memory array. If it were possible to reduce the space consumed by the Y-decoder circuitry, while not increasing the access time to the respective memory cells, a significant chip area reduction would result. This is because Y-decoder circuits, while often small in and of itself, permeates complex memory array circuits. A percentage decrease in each of these circuits could result in a decrease in the area for the memory array circuit. No known architecture, however, effectively reduces the Y-decoder circuit space, without compromising important memory array circuit performance characteristics. In fact, no known practical Y-decoder circuit provides the combination of fast Y-select activation while permitting a reduced layout area.